Hello, my name is
Joydeep Kumar Devnath
Senior Design Engineer, ML Algorithms & Systems
- joydeepkrdevnath@gmail.com
- +91 8638452791
About me
Artist and AI/VLSI Engineer with a passion for math. Over 4+ years of industry experience, specializing in AI/Machine Learning (ML) algorithms and systems engineering through core research.
I design and code AI algorithms for hardware/software.
With years of experience as an artificial intelligence design engineer, my focus transcends traditional design realms.
My expertise spans compiler design and architecture, coding and training of deep learning models like transformer, BERT, GCN, Stable Diffusion, etc. Embracing coding guidelines like MISRA C and PEP8, I have architected different software libraries. In this fast-paced world, I believe in guiding collective efforts and empowering teams to achieve seamless collaboration. In the realm of cutting-edge innovations, I have pioneered a power-efficient algorithm for certain fused deep-learning layer operations for hardware accelerators. Additionally, I have contributed significantly to neural network quantization for hardware chips and deployed posit number system for efficient deep learning hardware utilization. Upon reviewing my portfolio, you’ll observe my involvement in several patented innovations, underscoring my proficiency in AI design.
Skills
My Experience
Senior Design Engineer, Machine Learning
I contribute to the Hexagon Tensor Processor (HTP) team, focusing on deep learning operation kernels and model graph optimization. HTP is the neural processing unit (NPU) designed from the ground up for generative AI, integrated into all Snapdragon chipsets, including the Snapdragon X Series. This role requires me to stay current with state-of-the-art deep learning and generative AI models.
Senior AI Design Engineer 1
I was a part of an esteemed multidisciplinary team with a focus on life sciences. Leading the software team involved in developing deep learning models, I was also engaged in architecting and designing a compiler for analog compute circuits in this domain.
AI Design Engineer
As a member of an exceptional research and development team under Prof. Boris Murmann, I contributed to patented AI-driven security algorithms. I innovated a power-efficient algorithm for certain fused deep learning layer operations for hardware and filed for a patent (see portfolio). My other contributions span quantization of neural nets and posit numbers.
Junior Research Fellow
I collaborated within an exceptional research team. My focus included studying Neural Network Hardware accelerators, providing mathematical insights into Binary Neural Nets, co-designing a specialized memory architecture, and publishing a paper (see portfolio). I delved into Capsule Networks and explored reinforcement learning.