About
About me
An artist at heart and engineer by training, passionate about AI, ML graph compilers, and VLSI architectures.
AI algorithms and VLSI
With a strong foundation in Deep Learning, I focus on developing intelligent systems that leverage Generative AI models, model graph compilers, and data-driven optimization. My parallel experience in VLSI engineering supports the design of efficient hardware systems, enabling practical deployment of advanced AI solutions. My work bridges Gen AI and hardware for real-world impact.
My Skills
Experience
Senior Design Engineer, Machine Learning
I work on the Hexagon Tensor Processor (HTP) — a neural processing unit (NPU) purpose-built for accelerating Generative AI workloads across Snapdragon platforms, including the flagship Snapdragon X Series. My contributions span developing deep learning operation kernels, optimizing model graphs, and writing backend IR code that integrates with the HTP compiler pipeline. This role demands continuous engagement with state-of-the-art models and techniques in deep learning and Gen AI, ensuring high-performance deployment on-device.
Senior AI Design Engineer 1
I was a part of an esteemed multidisciplinary team with a focus on life sciences. Leading the software team involved in developing deep learning models, I was also engaged in architecting and designing a compiler for analog compute circuits in this domain.
AI Design Engineer
As a member of an exceptional research and development team under Prof. Boris Murmann, I contributed to patented AI-driven security algorithms. I innovated a power-efficient algorithm for certain fused deep learning layer operations for hardware and filed for a patent (see portfolio). My other contributions span quantization of neural nets and posit numbers.
Junior Research Fellow
I collaborated within an exceptional research team. My focus included studying Neural Network Hardware accelerators, providing mathematical insights into Binary Neural Nets, co-designing a specialized memory architecture, and publishing a paper (see portfolio). I delved into Capsule Networks and explored reinforcement learning.
Education
M.Tech Electrical Engineering (Microelectronics and VLSI):
My thesis was on "Energy Efficient Architectures for Neural Networks," guided by Prof. Joycee Mekie. I derived a formula for minimum exponent size in floating-point weight representation, ensuring accuracy. Furthermore, I have provided a mathematical rationale for a specific correlation between the mantissa and the depth of a model, proposing methods to enhance resilience to bit errors. My academic background encompasses a diverse range of subjects, including Pattern Recognition, Machine Learning, Artificial Intelligence, 3D Computer Vision, VLSI Design, Physics of Transistors, and CMOS Analog IC Design.
B.E. Electronics and Telecommunication Engineering [Gold Medal]
My final year project was on "Prediction Of Water Usage Based On Weather Data Pattern Using Neural Network", guided by Prof. Rashi Borgohain and Mr. Tanmoy Goswami. I constructed a device with Raspberry Pi, interfaced sensors for soil type and water usage data, and implemented a neural network. I created a web interface with RESTful APIs for user interaction. Additionally, I worked on a project involving human presence detection with a robot (AmigoBot) using machine learning during an internship at IITG. Upon detection, the robot would go and collect litter as directed.